Continuously reducing the size of solid-state memory architecture is an effective way to increase the capacity of such memories for a given amount of circuit real estate. However, the resulting feature size can give rise to design and process challenges. For example, the resistive-capacitive delay along wordlines in a memory array can dramatically increase with feature size reduction, providing strong electrical coupling between adjacent wordlines. The effects can most easily be seen as a reduction of the read threshold voltage (Vt) margin. As the wordlines in an array (both selected and unselected) are driven to desired values at about the same time, the far end of selected wordlines is often coupled to a voltage that is significantly higher than the near end.
The Vt margin may shrink for at least two reasons. First, the wordline coupling magnitude can be highly dependent on the target read level voltage, increasing with lower read voltage levels. For example, in some memories, a read voltage level of 0.1 V gives a coupling differential of 1.7 V, while a read voltage level of 2.7 V provides a coupling differential of only 0.5 V. Second, the offset from the target read voltage at the far end of a selected wordline can also strongly depend on the read voltage level.
As the use of multi-level cell (MLC) memory architecture becomes increasingly popular, preserving adequate Vt margins takes on added significance, because multiple read level voltages can be used within the same memory cell. Conventional approaches include waiting for all wordlines to settle so that read voltage levels can be accurately assessed. However, this solution results in increasingly long read times, so that MLC read operations can take longer than read operations for single cells. Program-verify operations are also affected. Thus, there is a need for apparatus, systems, and methods that provide a mechanism to reduce the read time, and increase read reliability of memory arrays having single-level cell (SLC) and MLC architectures.